Scientists showcase Storage Memory Breakthrough storing 3 bits of data per cell using PCM Technology can speed up machine learning and access to the IoT, mobile phone apps and cloud storage
Scientists at IBM Research have demonstrated reliably storing 3 bits of data per cell using a relatively new memory technology known as phase-change memory (PCM). The current memory landscape spans from venerable DRAM to hard disk drives to ubiquitous flash. But in the last several years PCM has attracted the industry’s attention as a potential universal memory technology based on its combination of read/write speed, endurance, non-volatility and density. This research breakthrough provides fast and easy storage to capture the exponential growth of data from mobile devices and the IoT.
IBM scientists envision standalone PCM as well as hybrid applications, which combine PCM and flash storage together, with PCM as an extremely fast cache. For example, a mobile phone’s operating system could be stored in PCM, enabling the phone to launch in a few seconds. In the enterprise space, entire databases could be stored in PCM for blazing fast query processing for time-critical online applications, such as financial transactions. Machine learning algorithms using large datasets will also see a speed boost by reducing the latency overhead when reading the data between iterations.
According to the press release, previously scientists at IBM and other institutes have successfully demonstrated the ability to store 1 bit per cell in PCM, but today at the IEEE International Memory Workshop in Paris, IBM scientists are presenting, for the first time, successfully storing 3 bits per cell in a 64k-cell array at elevated temperatures and after 1 million endurance cycles.
At the 2016 OpenPOWER Summit in San Jose, CA, last month, IBM scientists demonstrated, for the first time, phase-change memory attached to POWER8-based servers (made by IBM and TYAN Computer Corp.) via the CAPI (Coherent Accelerator Processor Interface) protocol. This technology leverages the low latency and small access granularity of PCM, the efficiency of the OpenPOWER architecture and the CAPI protocol. In the demonstration the scientists measured very low and consistent latency for 128-byte read/writes between the PCM chips and the POWER8 processor, the release said.
To achieve multi-bit storage IBM scientists have developed two innovative enabling technologies: a set of drift-immune cell-state metrics and drift-tolerant coding and detection schemes. More specifically, the new cell-state metrics measure a physical property of the PCM cell that remains stable over time, and are thus insensitive to drift, which affects the stability of the cell’s electrical conductivity with time. To provide additional robustness of the stored data in a cell over ambient temperature fluctuations a novel coding and detection scheme is employed. This scheme adaptively modifies the level thresholds that are used to detect the cell’s stored data so that they follow variations due to temperature change. As a result, the cell state can be read reliably over long time periods after the memory is programmed, thus offering non-volatility.
Dr. Haris Pozidis, author of the paper and the manager of non-volatile memory research at IBM Research – Zurich said, “Phase change memory is the first instantiation of a universal memory with properties of both DRAM and flash, thus answering one of the grand challenges of our industry. Reaching 3 bits per cell is a significant milestone because at this density the cost of PCM will be significantly less than DRAM and closer to flash.”